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obsolete functional block diagram reference in transparent latches decoders and drivers switch network i out control amp out reference out control amp in r set latch enable ad9712b/ad9713b (msb) (lsb) digital inputs d 1 thru d 12 i out + control amp 16 14 19 26 17 18 28 24 1 11 20 internal voltage reference rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 12-bit, 100 msps d/a converters ad9712b/ad9713b one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features 100 msps update rate ecl/ttl compatibility sfdr @ 1 mhz: 70 dbc low glitch impulse: 28 pv-s fast settling: 27 ns low power: 725 mw 1/2 lsb dnl (b grade) 40 mhz multiplying bandwidth applications ate signal reconstruction arbitrary waveform generators digital synthesizers signal generators general description the ad9712b and ad9713b d/a converters are replacements for the ad9712 and ad9713 units which offer improved ac and dc performance. like their predecessors, they are 12-bit, high speed digital-to-analog converters fabricated in an advanced oxide isolated bipolar process. the ad9712b is an ecl- compatible device featuring update rates of 100 msps mini- mum; the ttl-compatible ad9713b will update at 80 msps minimum. designed for direct digital synthesis, waveform reconstruction, and high resolution imaging applications, both devices feature low glitch impulse of 28 pv-s and fast settling times of 27 ns. both units are characterized for dynamic performance and have excellent harmonic suppression. the ad9712b and ad9713b are available in 28-pin plastic dips and plccs, with an operating temperature range of C25 c to +85 c. both are also available for extended tempera- ture ranges of C55 c to +125 c in cerdips and 28-pin lcc packages.
obsolete ad9712b/ad9713bCspecifications electrical characteristics ad9712b/ad9713b ad9712b/ad9713b ad9712b/ad9713b ad9712b/ad9713b test an/ap bn/bp se/sq te/tq parameter (conditions) temp level min typ max min typ max min typ max min typ max units resolution 12 12 12 12 bits dc accuracy differential nonlinearity +25 c i C1.25 1.0 +1.25 C0.75 0.5 +0.75 C1.5 1.0 +1.5 C1.0 0.5 +1.0 lsb full vi C2.0 2.0 C1.5 1.5 C2.0 2.0 C1.5 1.5 lsb integral nonlinearity +25 c i C1.5 1.0 1.5 C1.0 0.75 1.0 C1.75 1.5 1.75 C1.25 1.0 1.25 lsb (best fit straight line) full vi C2.0 2.0 C1.75 1.75 C2.0 2.0 C1.75 1.75 lsb ad9712b ad9713b test all grades all grades parameter (conditions) temp level min typ max min typ max units initial offset error zero-scale offset error +25 c i 0.5 2.5 0.5 2.5 m a full vi 5.0 5.0 m a full-scale gain error 1 +25 c i 1.0 5 1.0 5 % full vi 8 8 % offset drift coefficient +25 c v 0.01 0.01 m a/ c reference/control amp internal reference voltage +25 c i C1.14 C1.18 C1.22 C1.14 C1.18 C1.22 v full vi C1.12 C1.24 C1.12 C1.24 v internal reference voltage drift full v 50 50 ppm/ c internal reference output current full iv C50 +500 C50 +500 m a amplifier input impedance +25 c v 50 50 k w amplifier bandwidth +25 c v 300 300 khz reference input 2 reference input impedance +25 cv 3 3 k w reference multiplying bandwidth 3 +25 c v 40 40 mhz dynamic performance full-scale output current 4 +25 c v 20.48 20.48 ma output compliance range +25 c iv C1.2 +2 C1.2 +2 v output resistance +25 c iv 2.0 2.5 3.0 2.0 2.5 3.0 k w output capacitance +25 c v 15 15 pf output update rate 5 +25 c iv 100 110 80 100 msps output settling time (t st ) 6 +25 c v 27 27 ns output propagation delay (t pd ) 7 +25 cv 6 7 ns glitch impulse 8 +25 c v 28 28 pv-s output rise time 9 +25 cv 2 2 ns output fall time 9 +25 cv 2 2 ns digital inputs logic 1 voltage full vi C1.0 C0.8 2.0 v logic 0 voltage full vi C1.7 C1.5 0.8 v logic 1 current full vi 20 20 m a logic 0 current full vi 10 600 m a input capacitance +25 cv 3 3 pf input setup time (t s ) 10 +25 c iv 0.5 C0.3 0.5 C0.3 ns full iv 0.8 0.8 ns input hold time (t h ) 11 +25 c iv 1.8 1.2 1.8 1.2 ns full iv 2.0 2.0 ns latch pulse width (t lpw ) (low) +25 c iv 2.5 1.7 2.5 1.7 ns (transparent) full 2.8 2.8 ns ac linearity 12 spurious-free dynamic range (sfdr) 1.23 mhz; 10 msps; 2 mhz span +25 c v 70 70 db 5.055 mhz; 20 msps; 2 mhz span +25 c v 72 72 db 10.1 mhz; 50 msps; 2 mhz span +25 c v 68 68 db 16 mhz; 40 msps; 10 mhz span +25 c v 68 68 db rev. b C2C [Cv s = C5.2 v; +v s = +5 v (ad9713b only); reference voltage = C1.2 v; r set = 7.5 k v ; v out = 0 v (virtual ground); unless otherwise noted]
obsolete ad9712b ad9713b test all grades all grades parameter (conditions) temp level min typ max min typ max units power supply 13 positive supply current (+5.0 v) +25 ci 6 12 ma full vi 14 ma negative supply current (C5.2 v) 14 +25 c i 140 178 145 184 ma full vi 183 188 ma nominal power dissipation +25 c v 728 784 mw power supply rejection radio (psrr) 15 +25 c i 30 100 30 100 m a/v notes 1 measured as error in ratio of full-scale current to current through r set (160 m a nominal); ratio is nominally 128. 2 full-scale variations among devices are higher when driving reference input directly. 3 frequency at which the gain is flat 0.5 db; r l = 50 w ; 50% modulation at midscale. 4 based on i fs = 128 (v ref /r set ) when using internal amplifier. 5 data registered into dac accurately at this rate; does not imply settling to 12-bit accuracy. 6 measured as voltage settling at midscale transition to 0.024%, r l = 50 w . 7 measured as the time between the 50% point of the falling edge of latch enable and the point where the output signal has left a 1 lsb error band around its previous value. 8 peak glitch impulse is measured as the largest area under a single positive or negative transient. 9 measured with r l = 50 w and dac operating in latched mode. 10 data must remain stable for specified time prior to falling edge of latch enable signal. 11 data must remain stable for specified time after rising edge of latch enable signal. 12 sfdr is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window, which is centered at the fundamental frequency and covers the indicated span. 13 supply voltages should remain stable within 5% for normal operation. 14 108 ma typ on digital Cv s , 37 ma typ on analog Cv s . 15 measured at 5% of +v s (ad9713b only) and Cv s (ad9712b or ad9713b) using external reference. specifications subject to change without notice. ordering guide temperature package package model range description option ad9712ban C25 c to +85 c 28-pin pdip n-28 ad9712bbn C25 c to +85 c 28-pin pdip n-28 ad9712bap C25 c to +85 c 28-pin plcc p-28a ad9712bbp C25 c to +85 c 28-pin plcc p-28a ad9712bsq/883b C55 c to +125 c 28-pin cerdip q-28 ad9712bse/883b C55 c to +125 c 28-pin lcc e-28a ad9712btq/883b C55 c to +125 c 28-pin cerdip q-28 ad9712bte/883b C55 c to +125 c 28-pin lcc e-28a ad9713ban C25 c to +85 c 28-pin pdip n-28 ad9713bbn C25 c to +85 c 28-pin pdip n-28 ad9713bap C25 c to +85 c 28-pin plcc p-28a ad9713bbp C25 c to +85 c 28-pin plcc p-28a ad9713bsq/883b C55 c to +125 c 28-pin cerdip q-28 ad9713bse/883b C55 c to +125 c 28-pin lcc e-28a ad9713btq/883b C55 c to +125 c 28-pin cerdip q-28 ad9713bte/883b C55 c to +125 c 28-pin lcc e-28a explanation of test levels test level i C 100% production tested. ii C 100% production tested at +25 c, and sample tested at specified temperatures. iii C sample tested only. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C all devices are 100% tested at +25 c. 100% production tested at temperature extremes for extended tempera- ture devices; sample tested at temperature extremes for commercial/industrial devices. absolute maximum ratings 1 positive supply voltage (+v s ) (ad9713b only) . . . . . . . +6 v negative supply voltage (Cv s ) . . . . . . . . . . . . . . . . . . . . . C7 v analog-to-digital ground voltage differential . . . . . . . . 0.5 v digital input voltages (d 1 Cd 12 , latch enable) ad9712b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to Cv s ad9713b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.5 v to +v s internal reference output current . . . . . . . . . . . . . . . . 500 m a control amplifier input voltage range . . . . . . . . . 0 v to C4 v control amplifier output current . . . . . . . . . . . . . . . 2.5 ma reference input voltage range (v ref ) . . . . . . . . . . . 0 v to Cv s analog output current . . . . . . . . . . . . . . . . . . . . . . . . . 30 ma operating temperature range ad9712b/ad9713ban/ap/bn/bp . . . . . . . C25 c to +85 c ad9712b/ad9713bse/sq/te/tq . . . . . . C55 c to +125 c maximum junction temperature 2 ad9712b/ad9713ban/ap/bn/bp . . . . . . . . . . . . . +150 c ad9712b/ad9713bse/sq/te/tq . . . . . . . . . . . . . +175 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . +300 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedances with parts soldered in place: 28-pin plastic dip: q ja = 37 c/w, q jc = 10 c/w; 28-pin plcc: q ja = 44 c/w, q jc = 14 c/w; cerdip: q ja = 32 c/w, q jc = 10 c/w; lcc: q ja = 41 c/w, q jc = 13 c/w. no air flow. ad9712b/ad9713b rev. b C3C
obsolete ad9712b/ad9713b rev. b C4C pin descriptions pin # name function 1C10 d 2 Cd 11 ten bits of twelve-bit digital input word. 11 d 12 (lsb) least significant bit (lsb) of digital input word. input coding vs. current output input code d 1 Cd 12 i out (ma) i out (ma) 1111111111 C20.475 0 0000000000 0 C20.475 12 digital Cv s one of two negative digital supply pins; nominally C5.2 v. 13 analog return analog ground return. this point and the reference side of the dac load resistors should be connected to the same potential (nominally ground). 14 i out analog current output; full-scale output occurs with digital inputs at all 1. 15 analog Cv s one of two negative analog supply pins; nominally C5.2 v. 16 i out complementary analog current output; zero scale output occurs with digital inputs at all 1. 17 reference in normally connected to control amp out (pin 18). direct line to dac current source network. voltage changes at this point have a direct effect on the full-scale output value of unit. full-scale current output = 128 (reference voltage/r set ) when using internal amplifier. 18 control amp out normally connected to reference input (pin 17). output of internal control amplifier, which provides a temperature-compensated drive level to the current switch network. 19 control amp in normally connected to reference out (pin 20) if not connected to external reference. 20 reference out normally connected to control amp in (pin 19). internal voltage reference, nominally C1.18 v. 21 digital Cv s one of two negative digital supply pins; nominally C5.2 v. 22 reference ground ground return for the internal voltage reference and amplifier. 23 digital +v s positive digital supply pin, used only on the ad9713b; nominally +5 v. no connection to this pin on ad9712b. 24 r set connection for external resistance reference. full-scale current out = 128 (reference voltage/ r set ) when using internal amplifier. nominally 7.5 k w . 25 analog Cv s one of two negative analog supply pins; nominally C5.2 v. 26 latch enable transparent latch control line. register is transparent when latch enable is low. 27 digital ground digital ground return. 28 d 1 (msb) most significant bit (msb) of digital input word. pin configurations plcc/lcc analog ? s r set digital +v s reference ground digital ? s reference out control amp in d (msb) 1 digital ground d 6 d 9 d 8 d 7 d 11 d 10 analog return digital ? s analog ? s i out reference in control amp out ad9712b ad9713b d 5 d 3 d 2 latch enable (not to scale) top view 5 6 7 8 9 10 11 28 27 26 1 2 3 4 25 24 23 22 21 20 19 12 13 14 15 16 17 18 d (lsb) 12 d 4 i out dip d 6 d 9 d 8 d 7 d 11 d 10 d 12 (lsb) d 5 d 3 d 4 d 2 analog return i out digital ? s d 1 (msb0) digital ground latch enable r set reference ground reference out control amp in i out reference in control amp out analog ? s digital +v s digital ? s analog ? s 1 2 3 7 28 27 26 22 8 9 10 21 20 19 11 12 18 17 4 5 25 24 6 23 top view (not to scale) 13 14 16 15 ad9712b ad9713b
obsolete ad9712b/ad9713b rev. b C5C die layout and metalization information die dimensions . . . . . . . . . . . . . . . . . 220 196 15 ( 2) mils pad dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 mils metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aluminum backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . none substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cv s passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nitride theory and applications the ad9 712b and ad9713b high speed digital-to-analog converters utilize most significant bit (msb) decoding and segmentation techniques to reduce glitch impulse and main- tain 12 -bit linearity without trimming. as shown in the functional block diagram, the design is based on four main subsections: the decoder/driver circuits, the transparent latches, the switch network, and the control am- plifier. an internal bandgap reference is also included to allow operation with a minimum of external components. digital inputs/timing the ad9712b employs single-ended ecl-compatible inputs for data inputs d 1 Cd 12 and latch enable. the internal ecl midpoint reference is designed to match 10k ecl device thresholds. on the ad9713b, a ttl translator is added at each input; with this exception, the ad9712b and ad9713b are identical. in the decoder/driver section, the four msbs (d 1 Cd 4 ) are decoded to 15 thermometer code lines. an equalizing delay is included for the eight least significant bits (lsbs) and latch enable. this delay minimizes data skew, and data setup and hold times at the latch inputs; this is important when operating the latches in the transparent mode. without the delay, skew caused by the decoding circuits would degrade glitch impulse. the latches operate in their transparent mode when latch enable (pin 26) is at logic level 0. the latches should be used to synchronize data to the current switches by applying a narrow latch enable pulse with proper data setup and hold times as shown in the timing diagram. an external latch at each data input, clocked out of phase with the latch enable, operates the ad9712b/ad9713b in a master slave (edge- triggered) mode. this is the optimum way to operate the dac because data is always stable at the dac input. an external latch eases timing constraints when using the converter. although the ad9712b/ad9713b chip is designed to provide isolation from digital inputs to the outputs, some coupling of digital transitions is inevitable, especially with ttl or cmos inputs applied to the ad9713b. digital feedthrough can be re- duced by forming a low-pass filter using a (200 w ) series resistor in series with the capacitance of each digital input; this rolls off the slew rate of the digital inputs. references as shown in the functional block diagram, the internal bandgap reference, control amplifier, and reference input are pinned out for maximum user flexibility when setting the reference. when using the internal reference, reference out (pin 20) should be connected to control amp in (pin 19). con- trol amp out (pin 18) should be connected to refer- ence in (pin 17) through a 20 w resistor. a 0.1 m f ceramic capacitor from pin 17 to Cv s (pin 15) improves settling by decoupling switching noise from the current sink base line. a reference current cell provides feedback to the control amp by sinking current through r set (pin 24). t s ? input setup time t lpw ? latch pulse width ? output propagation delay t pd t h ? input hold time t st ? output settling time output error error band t pd latch enable t st t lpw t s t h valid data t pd data inputs output latch enable timing diagram
obsolete ad9712b/ad9713b rev. b C6C the reference in pin can also be driven directly for wider bandwidth multiplying operation. the analog signal for this mode of operation must have a signal swing in the range of C3.75 v to C4.25 v. this can be implemented by capacitively coupling into reference in a signal with a dc bias of C3.75 v to C4.25 v, as shown in figure 3; or by driving reference in with a low impedance op amp whose signal swing is limited to the stated range. outputs as indicated earlier, d 1 Cd 4 (four msbs) are decoded and drive 15 discrete current sinks. d5 and d6 are binarily weighted; and d 7 Cd 12 are applied to the r-2r network. this segmented archi- tecture reduces frequency domain errors due to glitch impulse. reference in ad9712b ad9713b ? s ~ ?v ? s 17 figure 3. wideband multiplying circuit the switch network provides complementary current outputs i out and i out . these current outputs are based on statistical current source matching which provides 12-bit linearity without trim. current is steered to either i out or i out in proportion to the digital input code. the sum of the two currents is always equal to the full-scale output current minus one lsb. the current output can be converted to a voltage by resistive loading as shown in figure 4. both i out and i out should be loaded equally for best overall performance. the voltage which is developed is the product of the output current and the value of the load resistor. full-scale output current is determined by control amp in and r set according to the equation: i out ( fs) = ( control amp in/r set ) 128 the internal reference is nominally C1.18 v with a tolerance of 3.5% and typical drift over temperature of 50 ppm/ c. if greater accuracy or better temperature stability is required, an external reference can be utilized. the ad589 reference shown in figure 1 features 10 ppm/ c drift over temperatures from 0 c to +70 c. control amp in ad9712b ad9713b ad589 + r 1 ~ 11k ? s 19 figure 1. use of ad589 as external reference two modes of multiplying operation are possible with the ad9712b/ad9713b. signals with small signal bandwidths up to 300 khz and input swings of 100 mv, or dc signals from C0.6 v to C1.2 v can be applied to the control amp input as shown in figure 2. because the control amplifier is internally compensated, the 0.1 m f capacitor at pin 17 can be reduced to 0.01 m f to maximize the multiplying bandwidth. however, it should be noted that settling time for changes to the digital in- puts will be degraded. control amp in ad9712b ad9713b 19 24 17 18 18 reference in control amp out r set r set r t ?.6v to ?.2v 300 khz max figure 2. low frequency multiplying circuit
obsolete ad9712b/ad9713b rev. b C7C d (lsb) 12 d 6 d 9 d 8 d 7 d 11 d 10 d 5 d 3 d 4 d 2 analog return digital ? s d (msb) 1 latch enable r set reference ground reference out control amp in reference in control amp out analog ? s ad9712b ad9713b 0.1? 0.01? 20 w r l r l system ground digital ground ?.2v 13 22 27 3 4 26 11 5 6 7 8 9 10 14 i out 12,21 15,25 20 16 24 19 18 17 28 1 2 ecl drive logic 0.1? 0.01? 0.1? v out = i fs x r l i out figure 4. typical resistive load connection an operational amplifier can also be used to perform the i to v conversion of the dac output. figure 5 shows an example of a circuit which uses the ad9617, a high speed, current feedback amplifier. control amp in ad9712b ad9713b 19 20 14 16 10k 10k 400 r fb r 1 200 i fs i os ref out i out 25 r l i out + 1/2 ad708 r ff 25 v ?.048v out 100 r 2 + 1/2 ad708 + ad9617 12.5 figure 5. i/vconversion using current feedback dac current across feedback resistor r fb determines the ad9617 output swing. a current divider formed by r l and r ff limits the current used in the i-to-v conversion, and provides an output voltage swing within the specifications of the ad9617. current through r 2 provides dc offset at the output of the ad9617. adjusting the value of r 1 adjusts the value of offset current. this offset current is based on the reference of the ad9712b/ad9713b, to avoid coupling noise into the output signal. the resistor values in figure 5 provide a 4.096 v swing, cen- tered at ground, at the output of the ad9617 amplifier. power and grounding maintaining low noise on power supplies and ground is critical for obtaining optimum results with the ad9712b or ad9713b. dacs are most often used in circuits which are predominantly digital. to preserve 12-bit performance, especially at conversion speeds up to 100 msps, special precautions are necessary for power supplies and grounding. ideally, the dac should have a separate analog ground plane. all ground pins of the dac, as well as reference and analog output components, should be tied directly to this analog ground plane. the dacs ground plane should be connected to the system ground plane at a single point. ferrite beads such as the stackpole 57-1392 or amidon fb-43b-101, along with high frequency, low-inductance decou- pling capacitors, should be used for the supply connections to isolate digital switching currents from the dac supply pins. separate isolation networks for the digital and analog supply connections will further reduce supply noise coupling to the output. molded socket assemblies should be avoided even when prototyping circuits with the ad9712b or ad9713b. when the dac cannot be directly soldered into the board, individual pin sockets such as amp #6-330808-0 (knock-out end), or #60330808-3 (open end) should be used. these have much less effect on inter-lead capacitance than do molded assemblies. dds applications numerically controlled oscillators (ncos) are digital devices which generate samples of a sine wave. when the nco is com- bined with a high performance d/a converter (dac), the com- bination system is referred to as a direct digital synthesizer (dds). the digital samples generated by the nco are reconstructed by the dac and the resulting sine wave is usable in any system which requires a stable, spectrally pure, frequency-agile refer- ence. the dac is often the limiting factor in dds applications, since it is the only analog function in the circuit. the ad9712b/ ad9713b d/a converters offer the highest level of performance available for dds applications. dc linearity errors of a dac are the dominant effect in low- frequency applications and can affect both noise and harmonic content in the output waveform. differential nonlinearity (dnl) errors determine the quantization error between adja- cent codes, while integral nonlinearity (inl) is a measure of how closely the overall transfer function of the dac compares with an ideal device. together, these errors establish the limits of phase and amplitude accuracy in the output waveform.
obsolete ad9712b/ad9713b rev. b C8C numerically-controlled oscillator tuning word 12 phase accumulator 14 32 output sine data ttl register 12 system clock latch enable phase-to-amplitude conversion d d 1 12 ad9712b ad9713b d/a converter figure 6. direct digital synthesizer block diagram 90 100 10 0% 5mv/div 5ns/div figure 7. ad9712b/ad9713b glitch impulse 1ns/div 90 100 10 0% 200mv/div figure 8. rise and fall characteristics when the analog frequency (f a ) is exactly f c /n and n is an even integer, the dds continually uses a small subset of the available dac codes. the dnl of the converter is effectively the dnl error of the codes used, and is typically worse than the error measured against all available dac codes. this increase in dnl is translated into higher harmonic and noise levels at the output. glitch impulse, often considered a figure of merit in dds appli- cations, is simply the initial transient response of the dac as it moves between two output levels. this nonlinearity is com- monly associated with external data skew, but this effect is mini- mized by using the on-board registers of the ad9712 b/ad9713b converters (see digital inputs/timing section). the majority of the glitch impulse, shown below, is produced as the current in the r-2r ladder network settles, and is fairly constant over the full-scale range of the dac. the fast transients which form the glitch impulse appear as high-frequency spurs in the output spectrum. while it is difficult to predict the effects of glitch on the output waveform, slew rate limitations trans late directly into harm onics. this makes slew rate the dominant effect in ac linearity of the dac. applications in which the ratio of analog frequency (f a ) to clock frequency (f c ) is relatively high will benefit from the high s lew rate and low output capacitance of the ad9712b/ ad9713b devices. another concern in dds applications is the presence of aliased harmonics in the output spectrum. aliased harmonics appear as spurs in the output spectrum at frequencies which are deter- mined by: mfa nf c where m and n are integers. the effects of these spurs are most easily observed in applica- tions where f a is nearly equal to an integer fraction of the clock rate. this condition causes the aliased harmonics to fold near the fundamental output frequency (see performance curves.)
obsolete ad9712b/ad9713b rev. b C9C figure 9a. figure 9b. figure 9c. figure 9d. figure 9e. figure 9f. figure 9. typical spectral performance
obsolete ad9712b/ad9713b rev. b C10C figure 10a. figure 10b. figure 10c. figure 10d. figure 10e. figure 10. typical spectral performance
obsolete ad9712b/ad9713b rev. b C11C ecl input buffer reference input control amplifier input reference output full-scale current control loop ttl input buffer output circuit r-2r dac (for 6 lsbs) control amp output ecl in ?.2 v ecl v mid ?.2 v control amp in 19 control amp out ?.2 v 18 reference in ?.2 v 138 current sources 17 2.5k w ? s 16pf i out 16pf 2.5k w analog return 14 16 13 i out ?.2 v reference out 20 r r r r rr 2r 2r 2r 2r 2r r or analog return i out d 12 d 11 d 10 d 9 d 8 d 7 d 1 d 6 13 14 16 i out 10 k w ttl in +5v + v bias reference out control amp control amp out r set control amp in ?.2 v reference in 24 19 20 18 17 figure 11. equivalent circuits
obsolete ad9712b/ad9713b rev. b C12C outline dimensions dimensions shown in inches and (mm). c1635C24C3/92 printed in u.s.a. 28-pin plastic dip (suffix n) 0.140 (3.56) min 0.100 (2.54) bsc 28 1 15 14 0.550 (13.97) 0.530 (13.46) 1.565 (39.70) 1.380 (35.10) 0.250 (6.35) max 0.022 (0.558) 0.014 (0.356) 0.70 (1.77) max 0.625 (15.8) 0.600 (15.24) 0.015 (0.381) 0.008 (0.204) 0.060 (1.52) 0.015 (0.38) 28-pin cerdip (suffix q) 0.590 (14.93) 1.490 (37.84) max 28 1 15 14 0.026 (0.660) 0.014 (0.356) 0.07 (1.78) 0.03 (0.76) 0.610 (15.49) 0.500 (12.70) 0.620 (15.74) 0.018 (0.45) 0.008 (0.20) 15 0 glass sealant 0.098 (2.45) 0.110 (2.79) 0.22 (5.59) max 0.125 (3.175) min 28-pin plastic leaded chip carrier (suffix p) pin 1 identifier 4 26 5 11 25 19 12 18 0.430 (10.92) 0.390 (9.91) 0.050 (1.27) bsc 0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 0.456 (11.58) 0.450 (11.43) 0.495 (12.57) 0.485 (12.32) 0.456 (11.58) 0.450 (11.43) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.495 (12.57) 0.485 (12.32) 0.025 (0.63) 0.015 (0.38) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16) 0.180 (4.57) 0.165 (4.19) 28-pin lcc package (suffix e) 0.458 (11.63) 0.442 (11.23) 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) 0.055 (1.40) 0.045 (1.14) 0.100 (2.54) 0.064 (1.63) 0.075 (1.91) ref bottom view 7 11 12 18 4 5 123 6 8 9 10 13 14 15 16 17 19 20 21 22 23 24 25 26 27 28

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